| Commit message (Collapse) | Author | Age | Files | Lines |
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Dual ported:
OUTREG_A -> OUT_REGMODE_A
OUTREG_B -> OUT_REGMODE_B
Pseudo dual ported:
OUTREG -> OUT_REGMODE_B
Single ported:
OUTREG -> OUT_REGMODE_A
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Add new definition for parse_lattice_param
Now parse_lattice_param is design to parse Property rather than search for it in cell.
This functionalty was move to parse_lattice_param_from_cell.
Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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Signed-off-by: gatecat <gatecat@ds0.me>
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This commit solves implicit cascading when clock signal drives DCC and logic
Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
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This uses a new data structure for net.users that allows gaps, so
removing a port from a net is no longer an O(n) operation on the number
of users the net has.
Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: gatecat <gatecat@ds0.me>
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The current version of Crosslink-NX Family Data Sheet lists the high
frequency oscillator maximum frequency as 481.5MHz (that is, 7% higher
than its nominal 450MHz):
https://www.latticesemi.com/-/media/LatticeSemi/Documents/DataSheets/CrossLink/FPGA-DS-02049-1-2-1-CrossLink-NX-Family.ashx?document_id=52780
Older documents listed a wider frequency range but ±7% is the range for
production parts.
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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macro
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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Signed-off-by: gatecat <gatecat@ds0.me>
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configuration
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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controlling the ratio of FFs that got glued to carry-chain clusters.
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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Signed-off-by: gatecat <gatecat@ds0.me>
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into IOLOGIC.
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: gatecat <gatecat@ds0.me>
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This replaces the arch-specific DelayInfo structure with new DelayPair
(min/max only) and DelayQuad (min/max for both rise and fall) structures
that form part of common code.
This further reduces the amount of arch-specific code; and also provides
useful data structures for timing analysis which will need to delay
with pairs/quads of delays as it is improved.
While there may be a small performance cost to arches that didn't
separate the rise/fall cases (arches that aren't currently separating
the min/max cases just need to be fixed...) in DelayInfo, my expectation
is that inlining will mean this doesn't make much difference.
Signed-off-by: gatecat <gatecat@ds0.me>
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Single argument constructors will silently convert to that type. This
is typically not the right thing to do. For example, the nexus and
ice40 arch_pybindings.h files were incorrectly parsing bel name strings,
etc.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Signed-off-by: D. Shah <dave@ds0.me>
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Signed-off-by: D. Shah <dave@ds0.me>
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Signed-off-by: David Shah <dave@ds0.me>
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Signed-off-by: David Shah <dave@ds0.me>
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Signed-off-by: David Shah <dave@ds0.me>
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Signed-off-by: David Shah <dave@ds0.me>
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Signed-off-by: David Shah <dave@ds0.me>
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Signed-off-by: David Shah <dave@ds0.me>
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Signed-off-by: David Shah <dave@ds0.me>
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Signed-off-by: David Shah <dave@ds0.me>
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