| Commit message (Collapse) | Author | Age | Files | Lines |
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Signed-off-by: gatecat <gatecat@ds0.me>
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Dual ported:
OUTREG_A -> OUT_REGMODE_A
OUTREG_B -> OUT_REGMODE_B
Pseudo dual ported:
OUTREG -> OUT_REGMODE_B
Single ported:
OUTREG -> OUT_REGMODE_A
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Support cross-domain clock relations in timing analyser
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Add new definition for parse_lattice_param
Now parse_lattice_param is design to parse Property rather than search for it in cell.
This functionalty was move to parse_lattice_param_from_cell.
Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
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Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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Signed-off-by: gatecat <gatecat@ds0.me>
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This commit solves implicit cascading when clock signal drives DCC and logic
Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
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This uses a new data structure for net.users that allows gaps, so
removing a port from a net is no longer an O(n) operation on the number
of users the net has.
Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: gatecat <gatecat@ds0.me>
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The current version of Crosslink-NX Family Data Sheet lists the high
frequency oscillator maximum frequency as 481.5MHz (that is, 7% higher
than its nominal 450MHz):
https://www.latticesemi.com/-/media/LatticeSemi/Documents/DataSheets/CrossLink/FPGA-DS-02049-1-2-1-CrossLink-NX-Family.ashx?document_id=52780
Older documents listed a wider frequency range but ±7% is the range for
production parts.
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nexus: Hotfix to disable unimplemented DCS routethru
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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macro
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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This makes predictDelay be based on an arbitrary belpin pair rather
than a arc of a net based on cell placement. This way 'what-if'
decisions can be evaluated without actually changing placement;
potentially useful for parallel placement.
A new helper predictArcDelay behaves like the old predictDelay to
minimise the impact on existing passes; only arches need be updated.
Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: gatecat <gatecat@ds0.me>
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configuration
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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controlling the ratio of FFs that got glued to carry-chain clusters.
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: gatecat <gatecat@ds0.me>
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nexus: Support for split Vcc routing
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Signed-off-by: gatecat <gatecat@ds0.me>
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nexus: Tweaks for router1 performance
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: gatecat <gatecat@ds0.me>
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into IOLOGIC.
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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