library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.mult_pkg.all; entity mult is port ( clk : in std_logic; rst : in std_logic; slot : in std_logic; a : in mult_i_t; y : out mult_o_t); end mult; architecture stru of mult is signal this_c : mult_reg_t; signal this_r : mult_reg_t := MULT_RESET; begin mult : process(this_r, slot, a) variable this : mult_reg_t; variable aa : std_logic_vector(31 downto 0); variable ah : std_logic_vector(30 downto 0); variable bh : std_logic_vector(15 downto 0); variable abh2 : std_logic_vector(32 downto 0); variable p2 : std_logic_vector(31 downto 0); variable p3 : std_logic_vector(31 downto 0); variable sgn : std_logic_vector(31 downto 0); variable pm : std_logic_vector(47 downto 0); variable c : std_logic_vector(63 downto 0); variable acc : std_logic_vector(63 downto 0); variable region: std_logic_vector(2 downto 0); variable sat : std_logic; variable code : mult_codeline_t; begin this := this_r; code := MULT_CODE(this.state); y.busy <= code.busy; -- FIXME: warning : combinatorial output -- operand intermediates, multiplier and input mux, lower 31bits of A and upper/lower 16bits of B aa := this.m1; if code.sela = MB then aa := this.mb; end if; ah := aa(30 downto 0); if code.size = B16 then ah(30 downto 15) := (others => '0'); end if; bh := this.m2(15 downto 0); if code.size = B16 then bh(15) := '0'; elsif code.shift = '1' then bh := '0' & this.m2(30 downto 16); end if; -- partial product adder input mux if code.size = B16 then abh2 := '0' & x"0000" & (aa(15) and this.m2(15)) & this.abh(29 downto 15); elsif this.shift = '0' then abh2 := '0' & this.abh(46 downto 15); else abh2 := '0' & (aa(31) and this.m2(31)) & this.abh(45 downto 15); end if; -- partial products adders p2 := (others => '0'); if aa(31) = '1' and code.shift = '1' then p2 := '0' & this.m2(30 downto 0); end if; if aa(15) = '1' and code.size = B16 then p2 := x"0000" & '0' & this.m2(14 downto 0); end if; p3 := (others => '0'); if this.m2(31) = '1' and code.shift = '1' then p3 := '0' & aa(30 downto 0); end if; if this.m2(15) = '1' and code.size = B16 then p3 := x"0000" & '0' & aa(14 downto 0); end if; if code.sign = 1 then sgn := (others => '1'); else sgn := (others => '0'); end if; pm := std_logic_vector(unsigned(abh2) + unsigned(sgn(0) & (this.p23 xor sgn)) + code.sign) & this.abh(14 downto 0); this.p23 := std_logic_vector(unsigned(p2) + unsigned(p3)); if this.shift = '0' then if pm(47) = '1' and code.size = B16 then c := x"ffff" & pm; else c := x"0000" & pm; end if; else c := pm & x"0000"; end if; -- accumulator acc := std_logic_vector(unsigned(c) + unsigned((this.mach and to_slv(code.use_h, 32)) & this.macl)); -- saturate sat := '1'; region := (others => '0'); case this.result_op is when IDENTITY => sat := '0'; when SATURATE64 => if acc(63) = '0' and acc(62 downto 47) /= x"0000" then region(0) := '1'; elsif acc(63) = '1' and acc(62 downto 47) /= x"ffff" then region(0) := '1'; end if; region(2 downto 1) := this.mach(31) & acc(63); if c(63) = '0' then case region is when "001" | "010" | "011" | "101" => acc := P48MAX; when "111" => acc := N48MAX; wh

for i in range(1, 10):
    print i