fpga_interchange/examples/archcheck/test_data.yaml


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pip_test:
    - src_wire: CLBLM_R_X11Y93/CLBLM_L_D3
      dst_wire: SLICE_X15Y93.SLICEL/D3
bel_pin_test:
    - bel: SLICE_X15Y93.SLICEL/D6LUT
      pin: A3
      wire: SLICE_X15Y93.SLICEL/D3