blob: 245aab04821269eba92c37ee78a879505709b96a (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
|
yosys -import
read_verilog counter.v
synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp
techmap -map ../remap.v
# opt_expr -undriven makes sure all nets are driven, if only by the $undef
# net.
opt_expr -undriven
opt_clean
setundef -zero -params
write_json build/counter.json
|
