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path:
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/
fpga_interchange
/
examples
/
lut
/
lut.v
blob: ca18e665d7d71cd502d11a5540857a1f3bbbd2f7 (
plain
)
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module
top
(
input
i0
,
input
i1
,
output
o
);
assign
o
=
i0
|
i1
;
endmodule
