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path: root/generic/examples/bitstream.py
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from write_fasm import *
from simple_config import K

# Need to tell FASM generator how to write parameters
# (celltype, parameter) -> ParameterConfig
param_map = {
	("GENERIC_SLICE", "K"): ParameterConfig(write=False),
	("GENERIC_SLICE", "INIT"): ParameterConfig(write=True, numeric=True, width=2**K),
	("GENERIC_SLICE", "FF_USED"): ParameterConfig(write=True, numeric=True, width=1),

	("GENERIC_IOB", "INPUT_USED"): ParameterConfig(write=True, numeric=True, width=1),
	("GENERIC_IOB", "OUTPUT_USED"): ParameterConfig(write=True, numeric=True, width=1),
	("GENERIC_IOB", "ENABLE_USED"): ParameterConfig(write=True, numeric=True, width=1),
}

with open("blinky.fasm", "w") as f:
	write_fasm(ctx, param_map, f)
_init cns3xxx_l2x0_init(void); -#else -static inline void cns3xxx_l2x0_init(void) {} -#endif /* CONFIG_CACHE_L2X0 */ - void __init cns3xxx_map_io(void); void __init cns3xxx_init_irq(void); int __init cns3xxx_pcie_init(void); --- a/arch/arm/mach-cns3xxx/Kconfig +++ b/arch/arm/mach-cns3xxx/Kconfig @@ -2,6 +2,8 @@ config ARCH_CNS3XXX bool "Cavium Networks CNS3XXX family" if ARCH_MULTI_V6 select ARM_GIC select CPU_V6K + select ARCH_REQUIRE_GPIOLIB + select GENERIC_IRQ_CHIP select GENERIC_CLOCKEVENTS select MIGHT_HAVE_CACHE_L2X0 select MIGHT_HAVE_PCI --- a/arch/arm/mach-cns3xxx/Makefile +++ b/arch/arm/mach-cns3xxx/Makefile @@ -1,7 +1,7 @@ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include obj-$(CONFIG_ARCH_CNS3XXX) += cns3xxx.o -cns3xxx-y += core.o pm.o +cns3xxx-y += core.o pm.o gpio.o cns3xxx-$(CONFIG_ATAGS) += devices.o cns3xxx-$(CONFIG_PCI) += pcie.o cns3xxx-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o --- a/arch/arm/mach-cns3xxx/cns3xxx.h +++ b/arch/arm/mach-cns3xxx/cns3xxx.h @@ -68,8 +68,10 @@ #define SMC_PCELL_ID_3_OFFSET 0xFFC #define CNS3XXX_GPIOA_BASE 0x74000000 /* GPIO port A */ +#define CNS3XXX_GPIOA_BASE_VIRT 0xFB006000 #define CNS3XXX_GPIOB_BASE 0x74800000 /* GPIO port B */ +#define CNS3XXX_GPIOB_BASE_VIRT 0xFB007000 #define CNS3XXX_RTC_BASE 0x75000000 /* Real Time Clock */ --- a/arch/arm/mach-cns3xxx/core.c +++ b/arch/arm/mach-cns3xxx/core.c @@ -60,6 +60,16 @@ static struct map_desc cns3xxx_io_desc[] .pfn = __phys_to_pfn(CNS3XXX_PCIE1_IO_BASE), .length = SZ_16M, .type = MT_DEVICE, + }, { + .virtual = CNS3XXX_GPIOA_BASE_VIRT, + .pfn = __phys_to_pfn(CNS3XXX_GPIOA_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = CNS3XXX_GPIOB_BASE_VIRT, + .pfn = __phys_to_pfn(CNS3XXX_GPIOB_BASE), + .length = SZ_4K, + .type = MT_DEVICE, }, };