blob: 928d1ceabecd64aafa8f5cbea6ce867bd7a7d76f (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
|
library ieee;
use ieee.std_logic_1164.all;
-- We don't have VHDL primitives yet, so declare them in examples for now.
package components is
component OSCH
generic (
NOM_FREQ : string := "2.08"
);
port(
STDBY : in std_logic;
OSC : out std_logic;
SEDSTDBY : out std_logic
);
end component;
end components;
|
