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Diffstat (limited to 'src/vhdl-demo/top.vhd')
-rw-r--r-- | src/vhdl-demo/top.vhd | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/src/vhdl-demo/top.vhd b/src/vhdl-demo/top.vhd new file mode 100644 index 0000000..99d0293 --- /dev/null +++ b/src/vhdl-demo/top.vhd @@ -0,0 +1,40 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + + +entity top is + port ( + CLK100MHZ: in std_logic; + + -- various stuff defined in the xdc file needs to be defined somewhere + leds: out std_logic_vector(1 downto 0); + btns: in std_logic_vector(1 downto 0) + + ); +end top; + + +architecture rtl of top is + signal led: std_logic; +begin + resetLogic: process (CLK100MHZ) + variable i: unsigned(31 downto 0) := to_unsigned(0, 32); + begin + if rising_edge(CLK100MHZ) then + if i >= to_unsigned(100000000, 32) then + led <= not led; + i := to_unsigned(0,32); + else + i := i + 1; + end if; + end if; + end process; + + leds(0) <= led; + leds(1) <= not led; +end rtl; + + + + |