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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-27 09:24:32 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-27 09:24:32 -0700 |
| commit | 00387f39277ab817b3b17e72b59793e6d5dfcde8 (patch) | |
| tree | 834e46988a887bca6f97e4ec9cfbf3ee27707a19 | |
| parent | dc87372a97d515563ccccd517ef8f35662870fe6 (diff) | |
| download | yosys-00387f39277ab817b3b17e72b59793e6d5dfcde8.tar.gz yosys-00387f39277ab817b3b17e72b59793e6d5dfcde8.tar.bz2 yosys-00387f39277ab817b3b17e72b59793e6d5dfcde8.zip | |
Revert to using clean
| -rw-r--r-- | tests/sat/initval.ys | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/sat/initval.ys b/tests/sat/initval.ys index 3d88aa971..2079d2f34 100644 --- a/tests/sat/initval.ys +++ b/tests/sat/initval.ys @@ -1,4 +1,4 @@ read_verilog -sv initval.v -proc; +proc;; sat -seq 10 -prove-asserts |