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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-01 09:44:53 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-01 09:44:53 -0700 |
| commit | 0067dc44f3928833eede2b9bb40260be78e11a93 (patch) | |
| tree | 704121d7150d983ba3963840d067c6301b955554 | |
| parent | 7be8551c8db468546357d71c8e395c943460435b (diff) | |
| download | yosys-0067dc44f3928833eede2b9bb40260be78e11a93.tar.gz yosys-0067dc44f3928833eede2b9bb40260be78e11a93.tar.bz2 yosys-0067dc44f3928833eede2b9bb40260be78e11a93.zip | |
Move abc9 from yosys-0.8 to yosys-0.9 in CHANGELOG
| -rw-r--r-- | CHANGELOG | 16 |
1 files changed, 11 insertions, 5 deletions
@@ -3,6 +3,17 @@ List of major changes and improvements between releases ======================================================= +Yosys 0.9 .. Yosys 0.9-dev +-------------------------- + + * Various + - Added "write_xaiger" backend + - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs) + - Added "synth_xilinx -abc9" (experimental) + - Added "synth_ice40 -abc9" (experimental) + - Added "synth -abc9" (experimental) + + Yosys 0.8 .. Yosys 0.8-dev -------------------------- @@ -26,11 +37,6 @@ Yosys 0.8 .. Yosys 0.8-dev - Added "synth_xilinx -nocarry" - Added "synth_xilinx -nowidelut" - Added "synth_ecp5 -nowidelut" - - Added "write_xaiger" backend - - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs) - - Added "synth_xilinx -abc9" (experimental) - - Added "synth_ice40 -abc9" (experimental) - - Added "synth -abc9" (experimental) - "synth_xilinx" to now infer hard shift registers (-nosrl to disable) - Fixed sign extension of unsized constants with 'bx and 'bz MSB |