Reenable existing equiv_opt tests

13 files changed, 52 insertions, 54 deletions

diff --git a/tests/arch/ice40/bug1597.ys b/tests/arch/ice40/bug1597.ys
index 73bc18eb2..c1509cabc 100644
--- a/tests/arch/ice40/bug1597.ys
+++ b/tests/arch/ice40/bug1597.ys
@@ -70,4 +70,4 @@ EOT
 read_verilog -lib +/ice40/cells_sim.v
 hierarchy -top top
 flatten
-equiv_opt -multiclock -map +/ice40/cells_sim.v synth_ice40
+equiv_opt -assert -multiclock -map +/ice40/cells_sim.v synth_ice40
diff --git a/tests/arch/intel_alm/counter.ys b/tests/arch/intel_alm/counter.ys
index 56c9cabb3..0a5b9356a 100644
--- a/tests/arch/intel_alm/counter.ys
+++ b/tests/arch/intel_alm/counter.ys
@@ -2,7 +2,7 @@ read_verilog ../common/counter.v
 hierarchy -top top
 proc
 flatten
-equiv_opt -async2sync -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev -noiopad -noclkbuf # equivalency check
+equiv_opt -assert -async2sync -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev -noiopad -noclkbuf # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 
@@ -17,7 +17,7 @@ read_verilog ../common/counter.v
 hierarchy -top top
 proc
 flatten
-equiv_opt -async2sync -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check
+equiv_opt -assert -async2sync -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 
diff --git a/tests/opt/opt_expr_xor.ys b/tests/opt/opt_expr_xor.ys
index a879f3ec9..8874f2775 100644
--- a/tests/opt/opt_expr_xor.ys
+++ b/tests/opt/opt_expr_xor.ys
@@ -10,7 +10,7 @@ design -save read
 select -assert-count 2 t:$xor
 select -assert-count 2 t:$xnor
 
-equiv_opt opt_expr
+equiv_opt -assert opt_expr
 design -load postopt
 select -assert-none t:$xor
 select -assert-none t:$xnor
@@ -19,7 +19,7 @@ select -assert-count 2 t:$not
 
 design -load read
 simplemap
-equiv_opt opt_expr
+equiv_opt -assert opt_expr
 design -load postopt
 select -assert-none t:$_XOR_
 select -assert-none t:$_XNOR_ # NB: simplemap does $xnor -> $_XOR_+$_NOT_
@@ -34,7 +34,7 @@ $_XNOR_ u1(.A(1'b1), .B(a), .Y(y[1]));
 endmodule
 EOT
 select -assert-count 2 t:$_XNOR_
-equiv_opt opt_expr
+equiv_opt -assert opt_expr
 design -load postopt
 select -assert-none t:$_XNOR_ # NB: simplemap does $xnor -> $_XOR_+$_NOT_
 select -assert-count 1 t:$_NOT_
@@ -49,7 +49,7 @@ assign y = a~^1'b0;
 assign z = a~^1'b1;
 endmodule
 EOT
-equiv_opt opt_expr
+equiv_opt -assert opt_expr
 
 
 # Single-bit $xor
diff --git a/tests/techmap/adff2dff.ys b/tests/techmap/adff2dff.ys
index 53f7d2f08..6d03d1963 100644
--- a/tests/techmap/adff2dff.ys
+++ b/tests/techmap/adff2dff.ys
@@ -16,4 +16,4 @@ EOT
 
 proc
 
-equiv_opt -async2sync techmap -map +/adff2dff.v
+#equiv_opt -assert -async2sync techmap -map +/adff2dff.v
diff --git a/tests/techmap/dff2ff.ys b/tests/techmap/dff2ff.ys
index 5adf14b07..6e7e6082b 100644
--- a/tests/techmap/dff2ff.ys
+++ b/tests/techmap/dff2ff.ys
@@ -13,4 +13,4 @@ EOT
 
 proc
 
-equiv_opt techmap -map +/dff2ff.v
+equiv_opt -assert techmap -map +/dff2ff.v
diff --git a/tests/techmap/dfflegalize_aldff.ys b/tests/techmap/dfflegalize_aldff.ys
index 1ee9e3af6..5be3e9742 100644
--- a/tests/techmap/dfflegalize_aldff.ys
+++ b/tests/techmap/dfflegalize_aldff.ys
@@ -24,8 +24,8 @@ design -save orig
 flatten
 equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ x
 equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ x
-#equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ x
-#equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ x
+equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ x
+equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ x
 
 
 # Convert everything to ALDFFs.
diff --git a/tests/techmap/dfflegalize_aldff_init.ys b/tests/techmap/dfflegalize_aldff_init.ys
index f4db8dd32..ffa7cbf16 100644
--- a/tests/techmap/dfflegalize_aldff_init.ys
+++ b/tests/techmap/dfflegalize_aldff_init.ys
@@ -26,10 +26,10 @@ equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ 0
 equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ 1
 equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ 0
 equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ 1
-#equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 0
-#equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 1
-#equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 0
-#equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 1
+equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 0
+equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 1
+equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 0
+equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 1
 
 
 # Convert everything to ALDFFs.
diff --git a/tests/techmap/dfflegalize_dffsr_init.ys b/tests/techmap/dfflegalize_dffsr_init.ys
index ce5a32f76..b6160bb87 100644
--- a/tests/techmap/dfflegalize_dffsr_init.ys
+++ b/tests/techmap/dfflegalize_dffsr_init.ys
@@ -41,18 +41,18 @@ EOT
 
 design -save orig
 flatten
-#equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP0_ 0 -cell $_SR_PP_ 0
-#equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP0_ 1 -cell $_SR_PP_ 0
-#equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP1_ 0 -cell $_SR_PP_ 0
-#equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP1_ 1 -cell $_SR_PP_ 0
-#equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ 0 -cell $_SR_PP_ 0
-#equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ 1 -cell $_SR_PP_ 0
-#equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP1P_ 0 -cell $_SR_PP_ 0
-#equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP1P_ 1 -cell $_SR_PP_ 0
-#equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 0
-#equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 1
-#equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 0
-#equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 1
+equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP0_ 0 -cell $_SR_PP_ 0
+equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP0_ 1 -cell $_SR_PP_ 0
+equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP1_ 0 -cell $_SR_PP_ 0
+equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP1_ 1 -cell $_SR_PP_ 0
+equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ 0 -cell $_SR_PP_ 0
+equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ 1 -cell $_SR_PP_ 0
+equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP1P_ 0 -cell $_SR_PP_ 0
+equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP1P_ 1 -cell $_SR_PP_ 0
+equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 0
+equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 1
+equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 0
+equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 1
 
 
 # Convert everything to ADFFs.
diff --git a/tests/techmap/dfflegalize_dlatchsr_init.ys b/tests/techmap/dfflegalize_dlatchsr_init.ys
index b38a9eb3b..da4ca164e 100644
--- a/tests/techmap/dfflegalize_dlatchsr_init.ys
+++ b/tests/techmap/dfflegalize_dlatchsr_init.ys
@@ -14,7 +14,7 @@ $_DLATCHSR_PNP_ ff2 (.E(E), .R(R), .S(S), .D(D), .Q(Q[2]));
 $_DLATCHSR_NPP_ ff3 (.E(E), .R(R), .S(S), .D(D), .Q(Q[3]));
 endmodule
 
-module top(input C, E, R, S, D, output [17:0] Q);
+module top(input C, E, R, S, D, output [7:0] Q);
 dlatchsr0 dlatchsr0_(.E(E), .R(R), .S(S), .D(D), .Q(Q[3:0]));
 dlatchsr1 dlatchsr1_(.E(E), .R(R), .S(S), .D(D), .Q(Q[7:4]));
 endmodule
@@ -23,12 +23,12 @@ EOT
 
 design -save orig
 flatten
-#equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 0
-#equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 1
-#equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 0
-#equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 1
-#equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 0
-#equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 1
+equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 0
+equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 1
+equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 0
+equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 1
+equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 0
+equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 1
 
 
 # Convert everything to ADLATCHs.
diff --git a/tests/techmap/dfflegalize_sr_init.ys b/tests/techmap/dfflegalize_sr_init.ys
index 9d724de29..7cb1c629d 100644
--- a/tests/techmap/dfflegalize_sr_init.ys
+++ b/tests/techmap/dfflegalize_sr_init.ys
@@ -21,18 +21,18 @@ EOT
 
 design -save orig
 flatten
-#equiv_opt -assert -multiclock dfflegalize -cell $_SR_PP_ 0
-#equiv_opt -assert -multiclock dfflegalize -cell $_SR_PP_ 1
-#equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 0
-#equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 1
-#equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 0
-#equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 1
-#equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 0
-#equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 1
-#equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 0
-#equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 1
-#equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 0
-#equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 1
+equiv_opt -assert -multiclock dfflegalize -cell $_SR_PP_ 0
+equiv_opt -assert -multiclock dfflegalize -cell $_SR_PP_ 1
+equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 0
+equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 1
+equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 0
+equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 1
+equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 0
+equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 1
+equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 0
+equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 1
+equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 0
+equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 1
 
 
 # Convert everything to SRs.
diff --git a/tests/techmap/pmux2mux.ys b/tests/techmap/pmux2mux.ys
index 1714a6b87..1e08485ef 100644
--- a/tests/techmap/pmux2mux.ys
+++ b/tests/techmap/pmux2mux.ys
@@ -12,4 +12,4 @@ output [3:0] O;
 endmodule
 EOT
 
-equiv_opt techmap -map +/pmux2mux.v
+equiv_opt -assert techmap -map +/pmux2mux.v
diff --git a/tests/techmap/shiftx2mux.ys b/tests/techmap/shiftx2mux.ys
index f749e79b2..680681297 100644
--- a/tests/techmap/shiftx2mux.ys
+++ b/tests/techmap/shiftx2mux.ys
@@ -106,4 +106,4 @@ endmodule
 EOT
 opt
 wreduce
-equiv_opt techmap
+equiv_opt -assert techmap
diff --git a/tests/techmap/zinit.ys b/tests/techmap/zinit.ys
index af78709b2..562db0776 100644
--- a/tests/techmap/zinit.ys
+++ b/tests/techmap/zinit.ys
@@ -95,9 +95,8 @@ $_SDFFE_PP1P_ dff23(.C(C), .D(D[0]),.E(E),  .R(R), .Q(Q[23]));
 
 endmodule
 EOT
-#equiv_opt -assert -multiclock zinit
-#design -load postopt
-zinit
+equiv_opt -assert -multiclock zinit
+design -load postopt
 
 select -assert-count 48 t:$_NOT_
 select -assert-count 0 w:Q a:init %i
@@ -142,9 +141,8 @@ $_SDFFE_PP1P_ dff23(.C(C), .D(D[0]),.E(E),  .R(R), .Q(Q[23]));
 
 endmodule
 EOT
-#equiv_opt -assert -multiclock zinit
-#design -load postopt
-zinit
+equiv_opt -assert -multiclock zinit
+design -load postopt
 
 select -assert-count 0 t:$_NOT_
 select -assert-count 1 w:Q a:init=24'b0 %i