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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-15 21:56:45 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-15 21:56:45 -0700 |
| commit | 0391499e46cd69cf809fe911fa7798b1ae994540 (patch) | |
| tree | 32708f4d4386049a668e9eb4e88be5b4d53bed03 | |
| parent | fecafb2207efc772fec49b357bc6e20ca6a25aca (diff) | |
| parent | dca45c0888c44857038bd65b6f51f6d9f67b169f (diff) | |
| download | yosys-0391499e46cd69cf809fe911fa7798b1ae994540.tar.gz yosys-0391499e46cd69cf809fe911fa7798b1ae994540.tar.bz2 yosys-0391499e46cd69cf809fe911fa7798b1ae994540.zip | |
Merge remote-tracking branch 'origin/master' into xaig
| -rw-r--r-- | README.md | 4 | ||||
| -rw-r--r-- | passes/proc/proc_rmdead.cc | 2 | ||||
| -rw-r--r-- | tests/various/muxcover.ys | 5 |
3 files changed, 5 insertions, 6 deletions
@@ -312,10 +312,10 @@ Verilog Attributes and non-standard features passes to identify input and output ports of cells. The Verilog backend also does not output blackbox modules on default. -- The ``dynports'' attribute is used by the Verilog front-end to mark modules +- The ``dynports`` attribute is used by the Verilog front-end to mark modules that have ports with a width that depends on a parameter. -- The ``hdlname'' attribute is used by some passes to document the original +- The ``hdlname`` attribute is used by some passes to document the original (HDL) name of a module when renaming a module. - The ``keep`` attribute on cells and wires is used to mark objects that should diff --git a/passes/proc/proc_rmdead.cc b/passes/proc/proc_rmdead.cc index d2f8d9ead..7c334e661 100644 --- a/passes/proc/proc_rmdead.cc +++ b/passes/proc/proc_rmdead.cc @@ -34,7 +34,7 @@ void proc_rmdead(RTLIL::SwitchRule *sw, int &counter) for (size_t i = 0; i < sw->cases.size(); i++) { - bool is_default = GetSize(sw->cases[i]->compare) == 0 || GetSize(sw->signal) == 0; + bool is_default = GetSize(sw->cases[i]->compare) == 0 && (!pool.empty() || GetSize(sw->signal) == 0); for (size_t j = 0; j < sw->cases[i]->compare.size(); j++) { RTLIL::SigSpec sig = sw->cases[i]->compare[j]; diff --git a/tests/various/muxcover.ys b/tests/various/muxcover.ys index 594e62af6..7ac460f13 100644 --- a/tests/various/muxcover.ys +++ b/tests/various/muxcover.ys @@ -8,13 +8,12 @@ read_verilog -formal <<EOT 3'b?1?: Y = B; 3'b1??: Y = C; 3'b000: Y = D; - default: Y = 'bx; endcase endmodule EOT -## Example usage for "pmuxtree" and "muxcover" +## Examle usage for "pmuxtree" and "muxcover" proc pmuxtree @@ -36,7 +35,7 @@ read_verilog -formal <<EOT 3'b010: Y = B; 3'b100: Y = C; 3'b000: Y = D; - default: Y = 'bx; + default: Y = 'bx; endcase endmodule EOT |