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| author | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-04 11:09:59 +0200 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-04 11:09:59 +0200 |
| commit | 03a3deec43ef4e92b251ea4bceaadc77c8044df0 (patch) | |
| tree | 3c6c9bd7a3855ab42333e51848ead23472e9d718 | |
| parent | a5844e3ceb76152d1e87ad8fdf1c71553238ef64 (diff) | |
| download | yosys-03a3deec43ef4e92b251ea4bceaadc77c8044df0.tar.gz yosys-03a3deec43ef4e92b251ea4bceaadc77c8044df0.tar.bz2 yosys-03a3deec43ef4e92b251ea4bceaadc77c8044df0.zip | |
Cleanup and formating
| -rw-r--r-- | tests/anlogic/add_sub.ys | 2 | ||||
| -rw-r--r-- | tests/anlogic/counter.ys | 2 | ||||
| -rw-r--r-- | tests/anlogic/fsm.ys | 1 | ||||
| -rw-r--r-- | tests/anlogic/shifter.ys | 1 |
4 files changed, 4 insertions, 2 deletions
diff --git a/tests/anlogic/add_sub.ys b/tests/anlogic/add_sub.ys index 55c090506..994cd0d03 100644 --- a/tests/anlogic/add_sub.ys +++ b/tests/anlogic/add_sub.ys @@ -5,5 +5,5 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p cd top # Constrain all select calls below inside the top module select -assert-count 10 t:AL_MAP_ADDER select -assert-count 4 t:AL_MAP_LUT1 -select -assert-none t:AL_MAP_LUT1 t:AL_MAP_ADDER %% t:* %D +select -assert-none t:AL_MAP_LUT1 t:AL_MAP_ADDER %% t:* %D diff --git a/tests/anlogic/counter.ys b/tests/anlogic/counter.ys index 5210221e3..036fdba46 100644 --- a/tests/anlogic/counter.ys +++ b/tests/anlogic/counter.ys @@ -8,4 +8,4 @@ cd top # Constrain all select calls below inside the top module select -assert-count 9 t:AL_MAP_ADDER select -assert-count 8 t:AL_MAP_SEQ -select -assert-none t:SB_CARRY t:AL_MAP_SEQ t:AL_MAP_ADDER %% t:* %D +select -assert-none t:AL_MAP_SEQ t:AL_MAP_ADDER %% t:* %D diff --git a/tests/anlogic/fsm.ys b/tests/anlogic/fsm.ys index 76a5d3e43..452ef9251 100644 --- a/tests/anlogic/fsm.ys +++ b/tests/anlogic/fsm.ys @@ -11,4 +11,5 @@ select -assert-count 1 t:AL_MAP_LUT2 select -assert-count 5 t:AL_MAP_LUT5 select -assert-count 1 t:AL_MAP_LUT6 select -assert-count 6 t:AL_MAP_SEQ + select -assert-none t:AL_MAP_LUT2 t:AL_MAP_LUT5 t:AL_MAP_LUT6 t:AL_MAP_SEQ %% t:* %D diff --git a/tests/anlogic/shifter.ys b/tests/anlogic/shifter.ys index edd89b344..5eaed30a3 100644 --- a/tests/anlogic/shifter.ys +++ b/tests/anlogic/shifter.ys @@ -6,4 +6,5 @@ equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 8 t:AL_MAP_SEQ + select -assert-none t:AL_MAP_SEQ %% t:* %D |