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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-10 16:14:26 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-10 16:14:26 -0700 |
| commit | 04153c501128ae37c7ed1235266ab6b32902b878 (patch) | |
| tree | 281ad5c081978f4fb37881acad377c93b5f7bfc0 | |
| parent | 5c1271c51c41b8a067ecf6165d3e09a73eee5fb7 (diff) | |
| download | yosys-04153c501128ae37c7ed1235266ab6b32902b878.tar.gz yosys-04153c501128ae37c7ed1235266ab6b32902b878.tar.bz2 yosys-04153c501128ae37c7ed1235266ab6b32902b878.zip | |
Update CHANGELOG
| -rw-r--r-- | CHANGELOG | 5 |
1 files changed, 5 insertions, 0 deletions
@@ -38,6 +38,11 @@ Yosys 0.9 .. Yosys 0.9-dev - Improvements in pmgen: slices, choices, define, generate - Added "xilinx_srl" for Xilinx shift register extraction - Removed "shregmap -tech xilinx" (superseded by "xilinx_srl") + - Added +/mul2dsp.v for decomposing wide multipliers to custom-sized ones + - Added "xilinx_dsp" for Xilinx DSP packing + - "synth_xilinx" to now infer DSP blocks (-nodsp to disable) + - "synth_ecp5" to now infer DSP blocks (-nodsp to disable, experimental) + - "synth_ice40 -dsp" to infer DSP blocks Yosys 0.8 .. Yosys 0.9 ---------------------- |