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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-08 10:51:19 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-08 10:51:19 -0700 |
| commit | 07e50b9c256358b2800a5272258a083f7e4d67d3 (patch) | |
| tree | 666a3fe0136b198b225f51a59c7f411b98d66118 | |
| parent | 716024387468285f0d5ee2719b86fe6ddbfff93e (diff) | |
| download | yosys-07e50b9c256358b2800a5272258a083f7e4d67d3.tar.gz yosys-07e50b9c256358b2800a5272258a083f7e4d67d3.tar.bz2 yosys-07e50b9c256358b2800a5272258a083f7e4d67d3.zip | |
Only pack registers if {A,B,P}REG = 0, do not pack $dffe
| -rw-r--r-- | passes/pmgen/xilinx_dsp.pmg | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg index a97ab4dd5..6fd1207fa 100644 --- a/passes/pmgen/xilinx_dsp.pmg +++ b/passes/pmgen/xilinx_dsp.pmg @@ -8,9 +8,10 @@ match dsp endmatch match ffA - select ffA->type.in($dff, $dffe) + select ffA->type.in($dff) // DSP48E1 does not support clock inversion select param(ffA, \CLK_POLARITY).as_bool() + filter param(dsp, \AREG).as_int() == 0 filter !port(dsp, \A).remove_const().empty() filter includes(port(ffA, \Q).to_sigbit_set(), port(dsp, \A).remove_const().to_sigbit_set()) optional @@ -22,9 +23,10 @@ code clock endcode match ffB - select ffB->type.in($dff, $dffe) + select ffB->type.in($dff) // DSP48E1 does not support clock inversion select param(ffB, \CLK_POLARITY).as_bool() + filter param(dsp, \BREG).as_int() == 0 filter !port(dsp, \B).remove_const().empty() filter includes(port(ffB, \Q).to_sigbit_set(), port(dsp, \B).remove_const().to_sigbit_set()) optional @@ -54,10 +56,11 @@ endcode match ffP if !sigPused.empty() - select ffP->type.in($dff, $dffe) + select ffP->type.in($dff) select nusers(port(ffP, \D)) == 2 // DSP48E1 does not support clock inversion select param(ffP, \CLK_POLARITY).as_bool() + filter param(dsp, \PREG).as_int() == 0 filter param(ffP, \WIDTH).as_int() >= GetSize(sigPused) filter includes(port(ffP, \D).to_sigbit_set(), sigPused.to_sigbit_set()) optional |