diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-18 17:50:11 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-18 17:50:11 -0700 |
| commit | 0919f36b88bed88e6dbfa23381540dc8ee035962 (patch) | |
| tree | 720ff0ec100d5133c011be13e046a14366c93f8f | |
| parent | cf66416110f60b7dce10a78960898ceb52f51626 (diff) | |
| download | yosys-0919f36b88bed88e6dbfa23381540dc8ee035962.tar.gz yosys-0919f36b88bed88e6dbfa23381540dc8ee035962.tar.bz2 yosys-0919f36b88bed88e6dbfa23381540dc8ee035962.zip | |
Missing close bracket
| -rw-r--r-- | techlibs/ice40/cells_sim.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v index a6f1fc9de..1d104c5d7 100644 --- a/techlibs/ice40/cells_sim.v +++ b/techlibs/ice40/cells_sim.v @@ -118,7 +118,7 @@ endmodule // SiliconBlue Logic Cells -(* abc_box_id = 22 * +(* abc_box_id = 22 *) module SB_LUT4 (output O, input I0, I1, I2, I3); parameter [15:0] LUT_INIT = 0; wire [7:0] s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0]; |