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| author | Clifford Wolf <clifford@clifford.at> | 2018-09-06 00:18:01 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2018-09-06 00:18:01 +0200 |
| commit | 12440fcc8f705c117b5f91fae24b7e5c4fbf8560 (patch) | |
| tree | a9955d3cd62399c8c4d5b612dd4717cc6729c2c1 | |
| parent | 5d9d22f66d512d33b2c1a13c4f1a20f944e6acc3 (diff) | |
| download | yosys-12440fcc8f705c117b5f91fae24b7e5c4fbf8560.tar.gz yosys-12440fcc8f705c117b5f91fae24b7e5c4fbf8560.tar.bz2 yosys-12440fcc8f705c117b5f91fae24b7e5c4fbf8560.zip | |
Add $lut support to Verilog back-end
Signed-off-by: Clifford Wolf <clifford@clifford.at>
| -rw-r--r-- | backends/verilog/verilog_backend.cc | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 44e4e5f97..d3262ec47 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -779,6 +779,19 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) return true; } + if (cell->type == "$lut") + { + f << stringf("%s" "assign ", indent.c_str()); + dump_sigspec(f, cell->getPort("\\Y")); + f << stringf(" = "); + dump_const(f, cell->parameters.at("\\LUT")); + f << stringf(" >> "); + dump_attributes(f, "", cell->attributes, ' '); + dump_sigspec(f, cell->getPort("\\A")); + f << stringf(";\n"); + return true; + } + if (cell->type == "$dffsr") { SigSpec sig_clk = cell->getPort("\\CLK"); |