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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-23 15:05:20 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-23 15:05:20 -0700 |
| commit | 151c5c96c0a85a1b69fc7824949ed89d70667059 (patch) | |
| tree | 4afab6f3f928f189771179afdf20bc553f753d2e | |
| parent | a37574ccbfe047c09a60bb6ee68b7b5e2ef61337 (diff) | |
| download | yosys-151c5c96c0a85a1b69fc7824949ed89d70667059.tar.gz yosys-151c5c96c0a85a1b69fc7824949ed89d70667059.tar.bz2 yosys-151c5c96c0a85a1b69fc7824949ed89d70667059.zip | |
Typo for Y_WIDTH
| -rw-r--r-- | techlibs/common/mul2dsp.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index cf9eeff6f..06ae3fc04 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -190,7 +190,7 @@ module \$__mul (A, B, Y); .B_SIGNED(B_SIGNED),
.A_WIDTH(A_WIDTH),
.B_WIDTH(B_WIDTH-(n-1)*(`DSP_B_MAXWIDTH-sign_headroom)),
- .Y_WIDTH(partial_Y_WIDTH)
+ .Y_WIDTH(last_Y_WIDTH)
) mul_last (
.A(A),
.B(B[B_WIDTH-1 : (n-1)*(`DSP_B_MAXWIDTH-sign_headroom)]),
|