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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-11 16:26:19 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-12-11 16:52:37 -0800 |
| commit | 151f7533e89d1a6db9c52b3c5d77adb2089db366 (patch) | |
| tree | 5e9f978115d448bf5271980f948bb3a0f22d495c | |
| parent | f022645cd2564ef47a6e8cf80c1452cd25f7ace2 (diff) | |
| download | yosys-151f7533e89d1a6db9c52b3c5d77adb2089db366.tar.gz yosys-151f7533e89d1a6db9c52b3c5d77adb2089db366.tar.bz2 yosys-151f7533e89d1a6db9c52b3c5d77adb2089db366.zip | |
Add testcase
| -rw-r--r-- | tests/various/bug1531.ys | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/tests/various/bug1531.ys b/tests/various/bug1531.ys new file mode 100644 index 000000000..542223030 --- /dev/null +++ b/tests/various/bug1531.ys @@ -0,0 +1,34 @@ +read_verilog <<EOT +module top (y, clk, w); + output reg y = 1'b0; + input clk, w; + reg [1:0] i = 2'b00; + always @(posedge clk) + // If the constant below is set to 2'b00, the correct output is generated. + // vvvv + for (i = 1'b0; i < 2'b01; i = i + 2'b01) + y <= w || i[1:1]; +endmodule +EOT + +synth +design -stash gate + +read_verilog <<EOT +module gold (y, clk, w); + input clk; + wire [1:0] i; + input w; + output y; + reg y = 1'h0; + always @(posedge clk) + y <= w; + assign i = 2'h0; +endmodule +EOT +proc gold + +design -import gate -as gate + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -seq 10 -verify -prove-asserts -show-ports miter |