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| author | Clifford Wolf <clifford@clifford.at> | 2013-08-20 09:46:05 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-08-20 09:46:05 +0200 |
| commit | 1af1cebb64b5d8d3f0a66d01d05762a15b3bc0db (patch) | |
| tree | d435ea29a37c2a4bc6a7e16bc54fa139e95505d3 | |
| parent | 0003743432dc804f65e61253ee71883175693d86 (diff) | |
| download | yosys-1af1cebb64b5d8d3f0a66d01d05762a15b3bc0db.tar.gz yosys-1af1cebb64b5d8d3f0a66d01d05762a15b3bc0db.tar.bz2 yosys-1af1cebb64b5d8d3f0a66d01d05762a15b3bc0db.zip | |
Minor fixes in abc build instructions and abc pass
| -rw-r--r-- | Makefile | 2 | ||||
| -rw-r--r-- | passes/abc/abc.cc | 8 |
2 files changed, 5 insertions, 5 deletions
@@ -86,7 +86,7 @@ yosys-svgviewer: libs/svgviewer/*.h libs/svgviewer/*.cpp abc: test -d abc || hg clone https://bitbucket.org/alanmi/abc abc - cd abc && hg pull && make + cd abc && hg pull && hg update && make cp abc/abc yosys-abc test: yosys diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc index c1f9eb2d9..41104ee99 100644 --- a/passes/abc/abc.cc +++ b/passes/abc/abc.cc @@ -457,21 +457,21 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std int buffer_pos = 0; if (!liberty_file.empty()) buffer_pos += snprintf(buffer+buffer_pos, 1024-buffer_pos, - "%s -c 'read_verilog %s/input.v; read_liberty %s; map; ", + "%s -s -c 'read_verilog %s/input.v; read_liberty %s; map; ", exe_file.c_str(), tempdir_name, liberty_file.c_str()); else if (!script_file.empty()) buffer_pos += snprintf(buffer+buffer_pos, 1024-buffer_pos, - "%s -c 'read_verilog %s/input.v; source %s; ", + "%s -s -c 'read_verilog %s/input.v; source %s; ", exe_file.c_str(), tempdir_name, script_file.c_str()); else if (lut_mode) buffer_pos += snprintf(buffer+buffer_pos, 1024-buffer_pos, - "%s -c 'read_verilog %s/input.v; read_lut %s/lutdefs.txt; if; ", + "%s -s -c 'read_verilog %s/input.v; read_lut %s/lutdefs.txt; if; ", exe_file.c_str(), tempdir_name, tempdir_name); else buffer_pos += snprintf(buffer+buffer_pos, 1024-buffer_pos, - "%s -c 'read_verilog %s/input.v; read_library %s/stdcells.genlib; map; ", + "%s -s -c 'read_verilog %s/input.v; read_library %s/stdcells.genlib; map; ", exe_file.c_str(), tempdir_name, tempdir_name); if (lut_mode) buffer_pos += snprintf(buffer+buffer_pos, 1024-buffer_pos, "write_blif %s/output.blif' 2>&1", tempdir_name); |