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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-12 12:27:07 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-12 12:27:07 -0700 |
| commit | 1c6f0cffd95876eac620bdfe9be50b366dabd8c6 (patch) | |
| tree | 42033db8fbbb1121d692650445412921cca4eff7 | |
| parent | f77da46a87b4c929548861c799a96564878b5a07 (diff) | |
| download | yosys-1c6f0cffd95876eac620bdfe9be50b366dabd8c6.tar.gz yosys-1c6f0cffd95876eac620bdfe9be50b366dabd8c6.tar.bz2 yosys-1c6f0cffd95876eac620bdfe9be50b366dabd8c6.zip | |
Cope with an output having same name as an input (i.e. CO)
| -rw-r--r-- | frontends/aiger/aigerparse.cc | 28 |
1 files changed, 23 insertions, 5 deletions
diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index b752d3127..0b0f6dd2e 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -460,12 +460,30 @@ next_line: log_assert(wire); log_assert(wire->port_output); - if (index == 0) - module->rename(wire, escaped_symbol); + if (index == 0) { + // Cope with the fact that a CO might be identical + // to a PO (necessary due to ABC); in those cases + // simply connect the latter to the former + RTLIL::Wire* existing = module->wire(escaped_symbol); + if (!existing) + module->rename(wire, escaped_symbol); + else { + wire->port_output = false; + module->connect(wire, existing); + } + } else if (index > 0) { - module->rename(wire, stringf("%s[%d]", escaped_symbol.c_str(), index)); - if (wideports) - wideports_cache[escaped_symbol] = std::max(wideports_cache[escaped_symbol], index); + std::string indexed_name = stringf("%s[%d]", escaped_symbol.c_str(), index); + RTLIL::Wire* existing = module->wire(indexed_name); + if (!existing) { + module->rename(wire, indexed_name); + if (wideports) + wideports_cache[escaped_symbol] = std::max(wideports_cache[escaped_symbol], index); + } + else { + module->connect(wire, existing); + wire->port_output = false; + } } } else |