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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-23 11:24:19 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-23 11:24:19 -0700 |
| commit | 20f4d191b53544049357401408d5d0c2b2ddcca4 (patch) | |
| tree | 90981083c75588e0a6ccc095f9d1809e2ddd30c6 | |
| parent | 0d0ad158984ddc3f66f895b6c18a62f250d2248e (diff) | |
| parent | 509c353fe981c95ca667a637bf2b47477962a60b (diff) | |
| download | yosys-20f4d191b53544049357401408d5d0c2b2ddcca4.tar.gz yosys-20f4d191b53544049357401408d5d0c2b2ddcca4.tar.bz2 yosys-20f4d191b53544049357401408d5d0c2b2ddcca4.zip | |
Merge branch 'master' into mwk/xilinx_bufgmap
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index f1e019d1e..aeef7f885 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -343,7 +343,7 @@ module RAM64X1D ( (* clkbuf_sink *) input WCLK, (* abc_scc_break *) - input WE, + input WE, input A0, A1, A2, A3, A4, A5, input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5 ); |