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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-10 18:06:33 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-10 18:06:33 -0700 |
| commit | 2217d59e299ce0cc15887d53308d7b7cb6400c52 (patch) | |
| tree | bb1f8356ce6be1a6362c45c5a5aa1aa75ad68432 | |
| parent | 1a49cf29d84c16f26b524b989e8fa07b3c6cab1d (diff) | |
| download | yosys-2217d59e299ce0cc15887d53308d7b7cb6400c52.tar.gz yosys-2217d59e299ce0cc15887d53308d7b7cb6400c52.tar.bz2 yosys-2217d59e299ce0cc15887d53308d7b7cb6400c52.zip | |
Add non-input bits driven by unrecognised cells as ci_bits
| -rw-r--r-- | backends/aiger/xaiger.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index a4ef89931..bad9322bb 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -229,7 +229,7 @@ struct XAigerWriter } if (is_output) { SigBit O = sigmap(b); - if (!input_bits.count(O) && !output_bits.count(O)) + if (!input_bits.count(O)) ci_bits.insert(O); } } |