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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-03 12:30:54 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-03 12:30:54 -0700 |
| commit | 257f7ff5f63635f0a754f34cf8af93ed06632b5b (patch) | |
| tree | d99d05d11377d563c7a8fce5225d67c0bea16d67 | |
| parent | 4da25c76b365b7c90a368c36def81d1122434b95 (diff) | |
| download | yosys-257f7ff5f63635f0a754f34cf8af93ed06632b5b.tar.gz yosys-257f7ff5f63635f0a754f34cf8af93ed06632b5b.tar.bz2 yosys-257f7ff5f63635f0a754f34cf8af93ed06632b5b.zip | |
When creating new holes cell, inherit parameters too
| -rw-r--r-- | backends/aiger/xaiger.cc | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 90fea2db1..818caebba 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -796,8 +796,10 @@ struct XAigerWriter RTLIL::Module* box_module = module->design->module(cell->type); int box_inputs = 0, box_outputs = 0; Cell *holes_cell = nullptr; - if (box_module->get_bool_attribute("\\whitebox")) + if (box_module->get_bool_attribute("\\whitebox")) { holes_cell = holes_module->addCell(cell->name, cell->type); + holes_cell->parameters = cell->parameters; + } // NB: Assume box_module->ports are sorted alphabetically // (as RTLIL::Module::fixup_ports() would do) |