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author | Marcelina Kościelnicka <mwk@0x04.net> | 2020-06-08 03:48:09 +0200 |
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committer | Marcelina Kościelnicka <mwk@0x04.net> | 2020-06-08 03:49:58 +0200 |
commit | 28b9f49c9411fdde8f9b1f5fac3f79d324676872 (patch) | |
tree | ee46a09d5e0666dc3ebbe425c946b4d0584d4d3d | |
parent | 210d129d9ab0f13db179ca556a414baa119b716a (diff) | |
download | yosys-28b9f49c9411fdde8f9b1f5fac3f79d324676872.tar.gz yosys-28b9f49c9411fdde8f9b1f5fac3f79d324676872.tar.bz2 yosys-28b9f49c9411fdde8f9b1f5fac3f79d324676872.zip |
fsm_extract: avoid calling log_signal to determine wire name
log_signal can result in a string with spaces (when bit selection is
involved), which breaks the rule of IdString not containing whitespace.
Instead, remove the sigspec from the name entirely — given that the
resulting wire will have no users, it will be removed later anyway,
so its name doesn't really matter.
Fixes #2118
-rw-r--r-- | passes/fsm/fsm_extract.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc index 3840aabc8..6f99886f0 100644 --- a/passes/fsm/fsm_extract.cc +++ b/passes/fsm/fsm_extract.cc @@ -394,7 +394,7 @@ static void extract_fsm(RTLIL::Wire *wire) RTLIL::Cell *cell = module->cells_.at(cellport.first); RTLIL::SigSpec port_sig = assign_map(cell->getPort(cellport.second)); RTLIL::SigSpec unconn_sig = port_sig.extract(ctrl_out); - RTLIL::Wire *unconn_wire = module->addWire(stringf("$fsm_unconnect$%s$%d", log_signal(unconn_sig), autoidx++), unconn_sig.size()); + RTLIL::Wire *unconn_wire = module->addWire(stringf("$fsm_unconnect$%d", autoidx++), unconn_sig.size()); port_sig.replace(unconn_sig, RTLIL::SigSpec(unconn_wire), &cell->connections_[cellport.second]); } } |