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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-19 10:00:53 -0700 |
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| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-19 10:00:53 -0700 |
| commit | 29e4c8bd06acf718328c76ec5d6c11e3274b21d1 (patch) | |
| tree | aa3aee95dd784bdc6cc964599d520366e92e5a78 | |
| parent | c36fca86f7d096e64b2a0eb6a3c4f5c427c7e537 (diff) | |
| download | yosys-29e4c8bd06acf718328c76ec5d6c11e3274b21d1.tar.gz yosys-29e4c8bd06acf718328c76ec5d6c11e3274b21d1.tar.bz2 yosys-29e4c8bd06acf718328c76ec5d6c11e3274b21d1.zip | |
Clarify with 'only'
| -rw-r--r-- | README.md | 2 |
1 files changed, 1 insertions, 1 deletions
@@ -420,7 +420,7 @@ Verilog Attributes and non-standard features - The port attribute ``abc_carry`` marks the carry-in (if an input port) and carry-out (if output port) ports of a box. This information is necessary for `abc9` to preserve the integrity of carry-chains. Specifying this attribute - onto a bus port will affect its most significant bit. + onto a bus port will affect only its most significant bit. Non-standard or SystemVerilog features for formal verification |