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author | Eddie Hung <eddie@fpgeh.com> | 2020-04-16 12:45:04 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2020-04-16 12:45:04 -0700 |
commit | 2ddfb61e65bb8299ba9bc09af9bb4636efc2ddb0 (patch) | |
tree | 9bbb42771700123332ba4b585edc32eaef2c674b | |
parent | 47c8ee7fe4c4935a11ed81b3d94069664e026dca (diff) | |
download | yosys-2ddfb61e65bb8299ba9bc09af9bb4636efc2ddb0.tar.gz yosys-2ddfb61e65bb8299ba9bc09af9bb4636efc2ddb0.tar.bz2 yosys-2ddfb61e65bb8299ba9bc09af9bb4636efc2ddb0.zip |
select: add test for not selecting inside black/white boxes
-rw-r--r-- | tests/select/blackboxes.ys | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/tests/select/blackboxes.ys b/tests/select/blackboxes.ys new file mode 100644 index 000000000..0031de194 --- /dev/null +++ b/tests/select/blackboxes.ys @@ -0,0 +1,21 @@ +read_verilog -specify <<EOT +module top(input a, b, output o); +assign o = a & b; +endmodule + +(* blackbox *) +module bb(input a, b, output o); +assign o = a | b; +specify + (a => o) = 1; +endspecify +endmodule + +(* whitebox *) +module wb(input a, b, output o); +assign o = a ^ b; +endmodule +EOT + +select -assert-count 1 c:* +select -assert-none t:* t:$and %d |