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authorEddie Hung <eddie@fpgeh.com>2020-04-16 12:45:04 -0700
committerEddie Hung <eddie@fpgeh.com>2020-04-16 12:45:04 -0700
commit2ddfb61e65bb8299ba9bc09af9bb4636efc2ddb0 (patch)
tree9bbb42771700123332ba4b585edc32eaef2c674b
parent47c8ee7fe4c4935a11ed81b3d94069664e026dca (diff)
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select: add test for not selecting inside black/white boxes
-rw-r--r--tests/select/blackboxes.ys21
1 files changed, 21 insertions, 0 deletions
diff --git a/tests/select/blackboxes.ys b/tests/select/blackboxes.ys
new file mode 100644
index 000000000..0031de194
--- /dev/null
+++ b/tests/select/blackboxes.ys
@@ -0,0 +1,21 @@
+read_verilog -specify <<EOT
+module top(input a, b, output o);
+assign o = a & b;
+endmodule
+
+(* blackbox *)
+module bb(input a, b, output o);
+assign o = a | b;
+specify
+ (a => o) = 1;
+endspecify
+endmodule
+
+(* whitebox *)
+module wb(input a, b, output o);
+assign o = a ^ b;
+endmodule
+EOT
+
+select -assert-count 1 c:*
+select -assert-none t:* t:$and %d