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| author | Jannis Harder <me@jix.one> | 2022-10-29 14:54:36 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-10-29 14:54:36 +0200 |
| commit | 31c15e5fa60b8cb47e7785fc420d90e860708034 (patch) | |
| tree | ba93d052c2c07b88541a9b06dee7b09158392dfb | |
| parent | 518194fac1d9915b82d0898177ef0546a2a69abe (diff) | |
| parent | aa7e7df19f21baff7e6ccfbf106c3b23ec9d4f6d (diff) | |
| download | yosys-31c15e5fa60b8cb47e7785fc420d90e860708034.tar.gz yosys-31c15e5fa60b8cb47e7785fc420d90e860708034.tar.bz2 yosys-31c15e5fa60b8cb47e7785fc420d90e860708034.zip | |
Merge pull request #3530 from jix/simlib-mux-fix
simlib: Simplify recently changed $mux model
| -rw-r--r-- | techlibs/common/simlib.v | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index 2fd75372d..e64697efb 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -1279,11 +1279,9 @@ parameter WIDTH = 0; input [WIDTH-1:0] A, B; input S; -output reg [WIDTH-1:0] Y; +output [WIDTH-1:0] Y; -always @* begin - assign Y = S ? B : A; -end +assign Y = S ? B : A; endmodule |