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| author | Clifford Wolf <clifford@clifford.at> | 2017-12-24 17:21:37 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-12-24 17:21:37 +0100 |
| commit | 34005348b65f69a2905357ee5877b5fbdd14da8c (patch) | |
| tree | 5d99c3f134070028d7ebe9fa40fb09f9f68b1594 | |
| parent | b66d50e62d0dcd2b495c360fa64f3c7b4017b842 (diff) | |
| download | yosys-34005348b65f69a2905357ee5877b5fbdd14da8c.tar.gz yosys-34005348b65f69a2905357ee5877b5fbdd14da8c.tar.bz2 yosys-34005348b65f69a2905357ee5877b5fbdd14da8c.zip | |
Bugfix in verilog_defaults argument parser
| -rw-r--r-- | frontends/verilog/verilog_frontend.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc index 19fc3c6af..e5917b97e 100644 --- a/frontends/verilog/verilog_frontend.cc +++ b/frontends/verilog/verilog_frontend.cc @@ -407,7 +407,7 @@ struct VerilogDefaults : public Pass { } virtual void execute(std::vector<std::string> args, RTLIL::Design*) { - if (args.size() == 0) + if (args.size() < 2) cmd_error(args, 1, "Missing argument."); if (args[1] == "-add") { |