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| author | Andrew Zonenberg <azonenberg@drawersteak.com> | 2017-08-07 20:20:17 -0700 |
|---|---|---|
| committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2017-08-14 10:45:39 -0700 |
| commit | 3618ca22181715cd24f6dca5911019d406f562e7 (patch) | |
| tree | e2dfce09f697dbde03823012dddf01f36891a383 | |
| parent | 4da1a327c056efc9bc5044804ab303422f495768 (diff) | |
| download | yosys-3618ca22181715cd24f6dca5911019d406f562e7.tar.gz yosys-3618ca22181715cd24f6dca5911019d406f562e7.tar.bz2 yosys-3618ca22181715cd24f6dca5911019d406f562e7.zip | |
Fixed typo in last commit
| -rw-r--r-- | techlibs/greenpak4/cells_sim_digital.v | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/techlibs/greenpak4/cells_sim_digital.v b/techlibs/greenpak4/cells_sim_digital.v index 0b83b7a2c..250f1da6a 100644 --- a/techlibs/greenpak4/cells_sim_digital.v +++ b/techlibs/greenpak4/cells_sim_digital.v @@ -119,7 +119,7 @@ module GP_COUNT14_ADV(input CLK, input RST, output reg OUT, //Combinatorially output underflow flag whenever we wrap low always @(*) begin if(UP) - OUT <= (count == 14'h4000); + OUT <= (count == 14'h3fff); else OUT <= (count == 14'h0); POUT <= count[7:0]; @@ -144,7 +144,7 @@ module GP_COUNT14_ADV(input CLK, input RST, output reg OUT, //Wrapping if(count == 0 && !UP) count <= COUNT_TO; - if(count == 14'h4000 && UP) + if(count == 14'h3fff && UP) count <= COUNT_TO; //Resets @@ -172,7 +172,7 @@ module GP_COUNT14_ADV(input CLK, input RST, output reg OUT, //Wrapping if(count == 0 && !UP) count <= COUNT_TO; - if(count == 14'h4000 && UP) + if(count == 14'h3fff && UP) count <= COUNT_TO; //Resets |