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| author | Eddie Hung <eddie@fpgeh.com> | 2020-04-20 20:56:38 -0700 |
|---|---|---|
| committer | Alberto Gonzalez <boqwxp@airmail.cc> | 2020-05-14 20:06:55 +0000 |
| commit | 36bb201dd9572f71c74d0987d8f42b19a6feaa9c (patch) | |
| tree | 25ce454845646d866e99aacbecb44479fb1af870 | |
| parent | ce62d0751ac25211cd468ae7026805e6933e0ce6 (diff) | |
| download | yosys-36bb201dd9572f71c74d0987d8f42b19a6feaa9c.tar.gz yosys-36bb201dd9572f71c74d0987d8f42b19a6feaa9c.tar.bz2 yosys-36bb201dd9572f71c74d0987d8f42b19a6feaa9c.zip | |
techmap: sort celltypeMap as it determines techmap order
| -rw-r--r-- | passes/techmap/techmap.cc | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 16bc9c803..8a8756757 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -1313,11 +1313,13 @@ struct TechmapPass : public Pass { celltypeMap[RTLIL::escape_id(q)].insert(module->name); free(p); } else { - std::string module_name = module->name.begins_with("\\$") ? + IdString module_name = module->name.begins_with("\\$") ? module->name.substr(1) : module->name.str(); celltypeMap[module_name].insert(module->name); } } + for (auto &i : celltypeMap) + i.second.sort(RTLIL::sort_by_id_str()); for (auto module : design->modules()) worker.module_queue.insert(module); @@ -1389,6 +1391,8 @@ struct FlattenPass : public Pass { dict<IdString, pool<IdString>> celltypeMap; for (auto module : design->modules()) celltypeMap[module->name].insert(module->name); + for (auto &i : celltypeMap) + i.second.sort(RTLIL::sort_by_id_str()); RTLIL::Module *top_mod = nullptr; if (design->full_selection()) |