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author | Miodrag Milanović <mmicko@gmail.com> | 2021-09-10 17:32:04 +0200 |
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committer | GitHub <noreply@github.com> | 2021-09-10 17:32:04 +0200 |
commit | 396918cc30a870e6d6049bdda1ddf8176ec5d116 (patch) | |
tree | 3a7fdd849cb41443ec26fc002c35fb9d8b3b4387 | |
parent | 33749f1e3aea0d0ee4d1b5b29eb00f3e4f4bae41 (diff) | |
parent | 4708907be8249d93a2aefbb36e4420a8b2054df3 (diff) | |
download | yosys-396918cc30a870e6d6049bdda1ddf8176ec5d116.tar.gz yosys-396918cc30a870e6d6049bdda1ddf8176ec5d116.tar.bz2 yosys-396918cc30a870e6d6049bdda1ddf8176ec5d116.zip |
Merge pull request #3001 from YosysHQ/claire/sigcheck
Add additional check to SigSpec
-rw-r--r-- | kernel/rtlil.cc | 16 | ||||
-rw-r--r-- | kernel/rtlil.h | 4 |
2 files changed, 14 insertions, 6 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 40b9b761a..a05023c52 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1753,7 +1753,7 @@ void RTLIL::Module::check() log_assert(!it.second->type.empty()); for (auto &it2 : it.second->connections()) { log_assert(!it2.first.empty()); - it2.second.check(); + it2.second.check(this); } for (auto &it2 : it.second->attributes) log_assert(!it2.first.empty()); @@ -1799,8 +1799,8 @@ void RTLIL::Module::check() for (auto &it : connections_) { log_assert(it.first.size() == it.second.size()); log_assert(!it.first.has_const()); - it.first.check(); - it.second.check(); + it.first.check(this); + it.second.check(this); } for (auto &it : attributes) @@ -4130,7 +4130,7 @@ RTLIL::SigSpec RTLIL::SigSpec::repeat(int num) const } #ifndef NDEBUG -void RTLIL::SigSpec::check() const +void RTLIL::SigSpec::check(Module *mod) const { if (width_ > 64) { @@ -4156,6 +4156,8 @@ void RTLIL::SigSpec::check() const log_assert(chunk.width >= 0); log_assert(chunk.offset + chunk.width <= chunk.wire->width); log_assert(chunk.data.size() == 0); + if (mod != nullptr) + log_assert(chunk.wire->module == mod); } w += chunk.width; } @@ -4166,6 +4168,12 @@ void RTLIL::SigSpec::check() const { cover("kernel.rtlil.sigspec.check.unpacked"); + if (mod != nullptr) { + for (size_t i = 0; i < bits_.size(); i++) + if (bits_[i].wire != nullptr) + log_assert(bits_[i].wire->module == mod); + } + log_assert(width_ == GetSize(bits_)); log_assert(chunks_.empty()); } diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 50707c0ae..06198b26a 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -965,9 +965,9 @@ public: unsigned int hash() const { if (!hash_) updhash(); return hash_; }; #ifndef NDEBUG - void check() const; + void check(Module *mod = nullptr) const; #else - void check() const { } + void check(Module *mod = nullptr) const { } #endif }; |