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| author | Clifford Wolf <clifford@clifford.at> | 2018-10-07 19:48:42 +0200 |
|---|---|---|
| committer | Jim Lawson <ucbjrl@berkeley.edu> | 2018-10-08 11:38:10 -0700 |
| commit | 3bb9288d65f547085b79fbaffb7046f336ff7f59 (patch) | |
| tree | bc60a2625efccaaab3fd5e548e0701179be84fd9 | |
| parent | 8e13f2913d3f493727d4e8774168aea2ac313f37 (diff) | |
| download | yosys-3bb9288d65f547085b79fbaffb7046f336ff7f59.tar.gz yosys-3bb9288d65f547085b79fbaffb7046f336ff7f59.tar.bz2 yosys-3bb9288d65f547085b79fbaffb7046f336ff7f59.zip | |
Improve Verific importer blackbox handling
Signed-off-by: Clifford Wolf <clifford@clifford.at>
| -rw-r--r-- | frontends/verific/verific.cc | 16 |
1 files changed, 14 insertions, 2 deletions
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 06d98611a..dba3b0f0c 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -118,6 +118,18 @@ RTLIL::SigBit VerificImporter::net_map_at(Net *net) return net_map.at(net); } +bool is_blackbox(Netlist *nl) +{ + if (nl->IsBlackBox()) + return true; + + const char *attr = nl->GetAttValue("blackbox"); + if (attr != nullptr && strcmp(attr, "0")) + return true; + + return false; +} + void VerificImporter::import_attributes(dict<RTLIL::IdString, RTLIL::Const> &attributes, DesignObj *obj) { MapIter mi; @@ -709,7 +721,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se netlist = nl; if (design->has(module_name)) { - if (!nl->IsOperator()) + if (!nl->IsOperator() && !is_blackbox(nl)) log_cmd_error("Re-definition of module `%s'.\n", nl->Owner()->Name()); return; } @@ -718,7 +730,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se module->name = module_name; design->add(module); - if (nl->IsBlackBox()) { + if (is_blackbox(nl)) { log("Importing blackbox module %s.\n", RTLIL::id2cstr(module->name)); module->set_bool_attribute("\\blackbox"); } else { |