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| author | Alberto Gonzalez <boqwxp@airmail.cc> | 2020-06-17 20:28:56 +0000 |
|---|---|---|
| committer | Alberto Gonzalez <boqwxp@airmail.cc> | 2020-06-19 18:16:33 +0000 |
| commit | 3ccdab940cd054d996a5ce94010918edd782cae0 (patch) | |
| tree | 20b447f4d8553aa589e90b133e23b2e4dee186b9 | |
| parent | d5d0cc88d272b85c3be3677993596dcfa82d579f (diff) | |
| download | yosys-3ccdab940cd054d996a5ce94010918edd782cae0.tar.gz yosys-3ccdab940cd054d996a5ce94010918edd782cae0.tar.bz2 yosys-3ccdab940cd054d996a5ce94010918edd782cae0.zip | |
rtlil: Add `Design::select()` for selecting whole modules.
| -rw-r--r-- | kernel/rtlil.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/kernel/rtlil.h b/kernel/rtlil.h index f3dc3af68..354823e3b 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -1061,6 +1061,13 @@ struct RTLIL::Design return selected_member(module->name, member->name); } + template<typename T1> void select(T1 *module) { + if (selection_stack.size() > 0) { + RTLIL::Selection &sel = selection_stack.back(); + sel.select(module); + } + } + template<typename T1, typename T2> void select(T1 *module, T2 *member) { if (selection_stack.size() > 0) { RTLIL::Selection &sel = selection_stack.back(); |