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| author | Jannis Harder <me@jix.one> | 2022-12-19 16:05:13 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-12-19 16:05:13 +0100 |
| commit | 3ebc50dee4007f8cca4ffc0e850bc3e86f7641f4 (patch) | |
| tree | 727967084bf0df0e75b4d5572559d0b071fdcaae | |
| parent | 69cbef9666a18bb7ce9fc7f6e87083ee12bd3177 (diff) | |
| parent | cf3570abde2351ae15892eb7318eccec48582a5d (diff) | |
| download | yosys-3ebc50dee4007f8cca4ffc0e850bc3e86f7641f4.tar.gz yosys-3ebc50dee4007f8cca4ffc0e850bc3e86f7641f4.tar.bz2 yosys-3ebc50dee4007f8cca4ffc0e850bc3e86f7641f4.zip | |
Merge pull request #3467 from jix/fix_cellarray_simplify
simplify: Do not recursively simplify AST_CELL within AST_CELLARRAY
| -rw-r--r-- | frontends/ast/simplify.cc | 2 | ||||
| -rw-r--r-- | tests/various/cellarray_array_connections.ys | 45 |
2 files changed, 47 insertions, 0 deletions
diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 349b87578..da7933d2f 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -1607,6 +1607,8 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, break; if (type == AST_GENBLOCK) break; + if (type == AST_CELLARRAY && children[i]->type == AST_CELL) + continue; if (type == AST_BLOCK && !str.empty()) break; if (type == AST_PREFIX && i >= 1) diff --git a/tests/various/cellarray_array_connections.ys b/tests/various/cellarray_array_connections.ys new file mode 100644 index 000000000..ef36a9a45 --- /dev/null +++ b/tests/various/cellarray_array_connections.ys @@ -0,0 +1,45 @@ +# Regression test for #3467 +read_verilog <<EOT + +module bit_buf ( + input wire bit_in, + output wire bit_out +); + assign bit_out = bit_in; +endmodule + +module top ( + input wire [3:0] data_in, + output wire [3:0] data_out +); + + wire [3:0] data [0:4]; + + assign data[0] = data_in; + assign data_out = data[4]; + + genvar i; + generate + for (i=0; i<=3; i=i+1) begin + bit_buf bit_buf_instance[3:0] ( + .bit_in(data[i]), + .bit_out(data[i + 1]) + ); + end + endgenerate +endmodule + +module top2 ( + input wire [3:0] data_in, + output wire [3:0] data_out +); + assign data_out = data_in; +endmodule + +EOT + +hierarchy +proc + +miter -equiv -make_assert -flatten top top2 miter +sat -prove-asserts -verify miter |