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| author | whitequark <whitequark@whitequark.org> | 2021-02-21 20:53:56 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-02-21 20:53:56 +0000 |
| commit | 3fee43cde0ec424e52ea62f78722b061aaac280a (patch) | |
| tree | c3fe7d79380e9bf2c73c56543f5461715e0a0395 | |
| parent | 127484e675538fbaeca1f6e53ba264a1f02e9cf6 (diff) | |
| parent | 220cb1f7bbf6405117b953526c50a21a5ef5788f (diff) | |
| download | yosys-3fee43cde0ec424e52ea62f78722b061aaac280a.tar.gz yosys-3fee43cde0ec424e52ea62f78722b061aaac280a.tar.bz2 yosys-3fee43cde0ec424e52ea62f78722b061aaac280a.zip | |
Merge pull request #2591 from zachjs/verilog-preproc-unapplied
verilog: error on macro invocations with missing argument lists
| -rw-r--r-- | frontends/verilog/preproc.cc | 11 | ||||
| -rw-r--r-- | tests/verilog/macro_unapplied.ys | 17 | ||||
| -rw-r--r-- | tests/verilog/macro_unapplied_newline.ys | 5 |
3 files changed, 32 insertions, 1 deletions
diff --git a/frontends/verilog/preproc.cc b/frontends/verilog/preproc.cc index c451c4c20..de707593f 100644 --- a/frontends/verilog/preproc.cc +++ b/frontends/verilog/preproc.cc @@ -477,7 +477,16 @@ static bool try_expand_macro(define_map_t &defines, std::string &tok) std::string name = tok.substr(1); std::string skipped_spaces = skip_spaces(); tok = next_token(false); - if (tok == "(" && body->has_args) { + if (body->has_args) { + if (tok != "(") { + if (tok.size() == 1 && iscntrl(tok[0])) { + char buf[5]; + snprintf(buf, sizeof(buf), "\\x%02x", tok[0]); + tok = buf; + } + log_error("Expected to find '(' to begin macro arguments for '%s', but instead found '%s'\n", + name.c_str(), tok.c_str()); + } std::vector<std::string> args; bool done = false; while (!done) { diff --git a/tests/verilog/macro_unapplied.ys b/tests/verilog/macro_unapplied.ys new file mode 100644 index 000000000..81eb10b8b --- /dev/null +++ b/tests/verilog/macro_unapplied.ys @@ -0,0 +1,17 @@ +logger -expect-no-warnings +read_verilog -sv <<EOT +`define MACRO(a = 1, b = 2) initial $display("MACRO(a = %d, b = %d)", a, b) +module top; + `MACRO(); +endmodule +EOT + +design -reset + +logger -expect error "Expected to find '\(' to begin macro arguments for 'MACRO', but instead found ';'" 1 +read_verilog -sv <<EOT +`define MACRO(a = 1, b = 2) initial $display("MACRO(a = %d, b = %d)", a, b) +module top; + `MACRO; +endmodule +EOT diff --git a/tests/verilog/macro_unapplied_newline.ys b/tests/verilog/macro_unapplied_newline.ys new file mode 100644 index 000000000..a3f88d5b4 --- /dev/null +++ b/tests/verilog/macro_unapplied_newline.ys @@ -0,0 +1,5 @@ +logger -expect error "Expected to find '\(' to begin macro arguments for 'foo', but instead found '\\x0a'" 1 +read_verilog -sv <<EOT +`define foo(a=1) (a) +`foo +EOT |