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| author | Eddie Hung <eddie@fpgeh.com> | 2019-11-22 15:35:08 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-11-22 15:35:51 -0800 |
| commit | 450ad0e9ba031fbeef904746ca773e3b0e21af8f (patch) | |
| tree | 763139dc1ef4f82635cedb979a02db32ce8a16c3 | |
| parent | 856a3dc98dcebdfdd331a5394a4556c00b4fcb8c (diff) | |
| download | yosys-450ad0e9ba031fbeef904746ca773e3b0e21af8f.tar.gz yosys-450ad0e9ba031fbeef904746ca773e3b0e21af8f.tar.bz2 yosys-450ad0e9ba031fbeef904746ca773e3b0e21af8f.zip | |
Add to CHANGELOG
| -rw-r--r-- | CHANGELOG | 1 |
1 files changed, 1 insertions, 0 deletions
@@ -53,6 +53,7 @@ Yosys 0.9 .. Yosys 0.9-dev - Added "check -mapped" - Added checking of SystemVerilog always block types (always_comb, always_latch and always_ff) + - Added "clkpart" pass Yosys 0.8 .. Yosys 0.9 ---------------------- |