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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-23 13:21:21 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-23 13:21:21 -0700 |
| commit | 455da572723e4f19ddc1d636b700a5fe1e975fbb (patch) | |
| tree | 9beeea8e4153d1ba7ab65b55d2bf00c8c8069b6f | |
| parent | 85d39653ac62fa4f1f809fb71b0df82a8bd01dfc (diff) | |
| download | yosys-455da572723e4f19ddc1d636b700a5fe1e975fbb.tar.gz yosys-455da572723e4f19ddc1d636b700a5fe1e975fbb.tar.bz2 yosys-455da572723e4f19ddc1d636b700a5fe1e975fbb.zip | |
Fix spacing
| -rw-r--r-- | techlibs/ecp5/cells_sim.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v index e2bf3c854..01b10f392 100644 --- a/techlibs/ecp5/cells_sim.v +++ b/techlibs/ecp5/cells_sim.v @@ -116,7 +116,7 @@ module TRELLIS_DPR16X4 ( input WCK, input [3:0] RAD, /* (* abc_arrival=<TODO> *) */ - output [3:0] DO + output [3:0] DO ); parameter WCKMUX = "WCK"; parameter WREMUX = "WRE"; |