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| author | SergeyDegtyar <sndegtyar@gmail.com> | 2019-09-10 08:36:59 +0300 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-17 17:10:02 +0200 |
| commit | 489444bcba0d54a45605872eb466792f07357f84 (patch) | |
| tree | 6328177a25d6137997c59b555c2a8209a2fa8a66 | |
| parent | 6331fa5b022b9e16f9392d9604a545f86dc13385 (diff) | |
| download | yosys-489444bcba0d54a45605872eb466792f07357f84.tar.gz yosys-489444bcba0d54a45605872eb466792f07357f84.tar.bz2 yosys-489444bcba0d54a45605872eb466792f07357f84.zip | |
Fix latches.ys test
| -rw-r--r-- | tests/xilinx/latches.ys | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/tests/xilinx/latches.ys b/tests/xilinx/latches.ys index 9ab562bcf..042ee2d4f 100644 --- a/tests/xilinx/latches.ys +++ b/tests/xilinx/latches.ys @@ -11,10 +11,9 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p design -load read synth_xilinx -#cd top - +flatten +cd top select -assert-count 1 t:LUT1 select -assert-count 2 t:LUT3 select -assert-count 3 t:$_DLATCH_P_ -#ERROR: Assertion failed: selection is not empty: t:LUT1 t:LUT3 t:$_DLATCH_P_ %% t:* %D -#select -assert-none t:LUT1 t:LUT3 t:$_DLATCH_P_ %% t:* %D +select -assert-none t:LUT1 t:LUT3 t:$_DLATCH_P_ %% t:* %D |