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| author | clairexen <claire@symbioticeda.com> | 2020-06-02 17:13:08 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-06-02 17:13:08 +0200 |
| commit | 4b3f48a7ec5d00395f50d46ed0222c01dee9fc09 (patch) | |
| tree | 3a3d30523ab32420c8027b920c679769a5844b9e | |
| parent | 2ed045738b1876f6439afd7f44c73100d7c96e99 (diff) | |
| parent | 0a88f002e50c0196175303068bcb3875a01d2c57 (diff) | |
| download | yosys-4b3f48a7ec5d00395f50d46ed0222c01dee9fc09.tar.gz yosys-4b3f48a7ec5d00395f50d46ed0222c01dee9fc09.tar.bz2 yosys-4b3f48a7ec5d00395f50d46ed0222c01dee9fc09.zip | |
Merge pull request #2102 from YosysHQ/tests_fix
allow range for mux test
| -rw-r--r-- | tests/arch/ice40/mux.ys | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/tests/arch/ice40/mux.ys b/tests/arch/ice40/mux.ys index 99822391d..2b661fd6b 100644 --- a/tests/arch/ice40/mux.ys +++ b/tests/arch/ice40/mux.ys @@ -35,6 +35,7 @@ proc equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux16 # Constrain all select calls below inside the top module -select -assert-count 11 t:SB_LUT4 +select -assert-min 11 t:SB_LUT4 +select -assert-max 12 t:SB_LUT4 select -assert-none t:SB_LUT4 %% t:* %D |