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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-17 13:20:29 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-17 13:20:29 -0700 |
| commit | 4b9eefe3b6fce79fc0b31a97efde3b5f1ba49cea (patch) | |
| tree | 7219ae7559bacd801d5d262cab7401245df97103 | |
| parent | 0c9cf892390941d52a3e35b29d509f4ee19ebae1 (diff) | |
| parent | 63fc879a5f698803d563a57275cc99a3df2d1414 (diff) | |
| download | yosys-4b9eefe3b6fce79fc0b31a97efde3b5f1ba49cea.tar.gz yosys-4b9eefe3b6fce79fc0b31a97efde3b5f1ba49cea.tar.bz2 yosys-4b9eefe3b6fce79fc0b31a97efde3b5f1ba49cea.zip | |
Merge remote-tracking branch 'origin/xaig' into xc7mux
| -rw-r--r-- | passes/techmap/abc9.cc | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 9c4e6bb39..184fbfaee 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -599,11 +599,12 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx; RTLIL::Cell *existing_cell = module->cell(c->name); if (existing_cell) { - cell->parameters = std::move(existing_cell->parameters); - cell->attributes = std::move(existing_cell->attributes); + cell->parameters = existing_cell->parameters; + cell->attributes = existing_cell->attributes; } else { - cell->parameters = std::move(c->parameters); + cell->parameters = c->parameters; + cell->attributes = c->attributes; } for (auto &conn : c->connections()) { RTLIL::SigSpec newsig; |