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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-20 18:27:16 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-20 18:27:16 -0700 |
| commit | 4cd1d21bfe412e9c6edb8aa74c19ee57370c56c4 (patch) | |
| tree | 1de98d40f2b3ecce91051f3be9ea559b3a477969 | |
| parent | 343039496baf434beca8c2fb3c275a60365f9496 (diff) | |
| download | yosys-4cd1d21bfe412e9c6edb8aa74c19ee57370c56c4.tar.gz yosys-4cd1d21bfe412e9c6edb8aa74c19ee57370c56c4.tar.bz2 yosys-4cd1d21bfe412e9c6edb8aa74c19ee57370c56c4.zip | |
Add (* abc_arrival=<int> *) doc
| -rw-r--r-- | README.md | 5 |
1 files changed, 5 insertions, 0 deletions
@@ -414,6 +414,11 @@ Verilog Attributes and non-standard features `abc9` to preserve the integrity of carry-chains. Specifying this attribute onto a bus port will affect only its most significant bit. +- The port attribute ``abc_arrival`` specifies an integer (for output ports + only) to be used as the arrival time of this sequential port. It can be used, + for example, to specify the clk-to-Q delay of a flip-flop for consideration + during techmapping. + Non-standard or SystemVerilog features for formal verification ============================================================== |