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| author | Clifford Wolf <clifford@clifford.at> | 2018-12-19 19:48:54 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-12-19 19:48:54 +0100 |
| commit | 4d84a456dcbf5dea7e689a05cb031a394cec447a (patch) | |
| tree | d85c745846e751f73a329d6f81c2953e211fe835 | |
| parent | 2d73e1b60a43f2a621b387768134b83054f59e89 (diff) | |
| parent | 7854d5ba217788bb66881237feac8ba2748758b9 (diff) | |
| download | yosys-4d84a456dcbf5dea7e689a05cb031a394cec447a.tar.gz yosys-4d84a456dcbf5dea7e689a05cb031a394cec447a.tar.bz2 yosys-4d84a456dcbf5dea7e689a05cb031a394cec447a.zip | |
Merge pull request #749 from Icenowy/anlogic-dram-fix
anlogic: fix dbits of Anlogic Eagle DRAM16X4
| -rw-r--r-- | techlibs/anlogic/drams.txt | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/anlogic/drams.txt b/techlibs/anlogic/drams.txt index 2bff14a03..eb94775ae 100644 --- a/techlibs/anlogic/drams.txt +++ b/techlibs/anlogic/drams.txt @@ -1,7 +1,7 @@ bram $__ANLOGIC_DRAM16X4 init 0 abits 4 - dbits 2 + dbits 4 groups 2 ports 1 1 wrmode 0 1 |