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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-24 22:12:50 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-24 22:12:50 -0700 |
| commit | 4fadb471a3028487d4b05b3e343b3be49349f78b (patch) | |
| tree | 64b7ff8e51930926a651b3861cbf3d2b90b1dff2 | |
| parent | a4a7e63d84dee73554d53587f38409e25db84b66 (diff) | |
| download | yosys-4fadb471a3028487d4b05b3e343b3be49349f78b.tar.gz yosys-4fadb471a3028487d4b05b3e343b3be49349f78b.tar.bz2 yosys-4fadb471a3028487d4b05b3e343b3be49349f78b.zip | |
Re-enable dist RAM boxes for ECP5
| -rw-r--r-- | techlibs/ecp5/cells_sim.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v index f66147323..0239d1afe 100644 --- a/techlibs/ecp5/cells_sim.v +++ b/techlibs/ecp5/cells_sim.v @@ -106,7 +106,7 @@ module PFUMX (input ALUT, BLUT, C0, output Z); endmodule // --------------------------------------- -//(* abc_box_id=2 *) +(* abc_box_id=2, abc_scc_break="DI" *) module TRELLIS_DPR16X4 ( input [3:0] DI, input [3:0] WAD, |