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| author | Graham Edgecombe <gpe@grahamedgecombe.com> | 2017-12-09 21:39:20 +0000 |
|---|---|---|
| committer | Graham Edgecombe <gpe@grahamedgecombe.com> | 2017-12-10 15:33:38 +0000 |
| commit | 52ace35a73839d661163206f123074368f751a09 (patch) | |
| tree | 2137bde09a962a4457077a84217f0a7d45d33ee3 | |
| parent | ba90e08398e3068a525c3704a069182a365474e8 (diff) | |
| download | yosys-52ace35a73839d661163206f123074368f751a09.tar.gz yosys-52ace35a73839d661163206f123074368f751a09.tar.bz2 yosys-52ace35a73839d661163206f123074368f751a09.zip | |
Remove trailing comma from SB_IO_OD port list
This isn't compatible with Icarus Verilog.
| -rw-r--r-- | techlibs/ice40/cells_sim.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v index b398c1886..2ace597b6 100644 --- a/techlibs/ice40/cells_sim.v +++ b/techlibs/ice40/cells_sim.v @@ -1193,7 +1193,7 @@ module SB_IO_OD ( input DOUT1, input DOUT0, output DIN1, - output DIN0, + output DIN0 ); parameter [5:0] PIN_TYPE = 6'b000000; parameter [0:0] NEG_TRIGGER = 1'b0; |