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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-29 09:58:00 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-29 09:58:00 -0700 |
| commit | 5a4011e8c9d2c7c94ccaa6ff80a1ca1290e1053b (patch) | |
| tree | 826831eb3086d3376a516286aef65877f67c510b | |
| parent | f3e150d9a5a71a554a99c619ae5389f687c381ef (diff) | |
| download | yosys-5a4011e8c9d2c7c94ccaa6ff80a1ca1290e1053b.tar.gz yosys-5a4011e8c9d2c7c94ccaa6ff80a1ca1290e1053b.tar.bz2 yosys-5a4011e8c9d2c7c94ccaa6ff80a1ca1290e1053b.zip | |
Fix "scc" call inside abc9 to consider all wires
| -rw-r--r-- | passes/techmap/abc9.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index a5d823139..ce27f7eea 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -75,7 +75,7 @@ inline std::string remap_name(RTLIL::IdString abc_name) void handle_loops(RTLIL::Design *design) { - Pass::call(design, "scc -set_attr abc_scc_id {}"); + Pass::call(design, "scc -set_attr abc_scc_id {} % w:*"); // For every unique SCC found, (arbitrarily) find the first // cell in the component, and select (and mark) all its output |