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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-30 14:38:06 -0700 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-17 17:10:02 +0200 |
| commit | 5b7bc3ab85d31920883995636d26dc5b971ca24d (patch) | |
| tree | 41fc76228ee5b2027ea2e12ab0cdf73de56ab341 | |
| parent | 08bd1816e39d2abfbe36ce0b58c0d4506db303e4 (diff) | |
| download | yosys-5b7bc3ab85d31920883995636d26dc5b971ca24d.tar.gz yosys-5b7bc3ab85d31920883995636d26dc5b971ca24d.tar.bz2 yosys-5b7bc3ab85d31920883995636d26dc5b971ca24d.zip | |
Update mul test to DSP48E1
| -rw-r--r-- | tests/xilinx/mul.ys | 11 |
1 files changed, 2 insertions, 9 deletions
diff --git a/tests/xilinx/mul.ys b/tests/xilinx/mul.ys index ec30c9c2c..f5306e848 100644 --- a/tests/xilinx/mul.ys +++ b/tests/xilinx/mul.ys @@ -4,12 +4,5 @@ equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -select -assert-count 12 t:LUT2 -select -assert-count 1 t:LUT3 -select -assert-count 6 t:LUT4 -select -assert-count 1 t:LUT5 -select -assert-count 33 t:LUT6 -select -assert-count 11 t:MUXCY -select -assert-count 1 t:MUXF7 -select -assert-count 12 t:XORCY -select -assert-none t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:XORCY %% t:* %D +select -assert-count 1 t:DSP48E1 +select -assert-none t:DSP48E1 %% t:* %D |