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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-17 12:14:55 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-17 12:14:55 -0700 |
| commit | 5ce672d1c502d24551e71a8296a672ff16411870 (patch) | |
| tree | 733893e04b56c3897126bf1473f38725166e9066 | |
| parent | 0c59bc0b75ba2985e6ae0806d410fe2fa1c94e37 (diff) | |
| parent | c15ee827f4a171abe3108dba8f9ad0d7078eb306 (diff) | |
| download | yosys-5ce672d1c502d24551e71a8296a672ff16411870.tar.gz yosys-5ce672d1c502d24551e71a8296a672ff16411870.tar.bz2 yosys-5ce672d1c502d24551e71a8296a672ff16411870.zip | |
Merge remote-tracking branch 'origin/xaig' into xaig_dff
| -rw-r--r-- | passes/techmap/abc9.cc | 2 | ||||
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 3 |
2 files changed, 3 insertions, 2 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 4e7bdfa8f..e234ab28d 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -29,7 +29,7 @@ "&st; &if -g -K 6; &dch -f; &if {W}; &save; &load; "\ "&st; &if -g -K 6; &synch2; &if {W}; &save; &load" #else -#define ABC_COMMAND_LUT "&st; &sweep; &scorr; "/*"&dc2; "*/"&retime; &dch -f; &ps -l; &if {W} {D} -v; "/*"&mfs; "*/"&ps -l" +#define ABC_COMMAND_LUT "&st; &sweep; &scorr; &dc2; &retime; &st; &dch -f; &ps -l; &if {W} {D} -v; "/*"&mfs; "*/"&ps -l" #endif diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index db43e13c1..d3f096220 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -25,7 +25,8 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN -#define XC7_WIRE_DELAY "160" +#define XC7_WIRE_DELAY "300" // Number with which ABC will map a 6-input gate + // to one LUT6 (instead of a LUT5 + LUT2) struct SynthXilinxPass : public ScriptPass { |