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authorEddie Hung <eddie@fpgeh.com>2019-11-26 11:57:26 -0800
committerEddie Hung <eddie@fpgeh.com>2019-11-26 23:26:25 -0800
commit5e487b103c3c1ed9f1fcaca21821466628b7ff80 (patch)
tree268fb77858ee14277f8a726eb93f3fc3290a7f57
parent435d33c37307563f193b8c798ad46ebb19cf4f07 (diff)
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Fix submod -hidden
-rw-r--r--passes/hierarchy/submod.cc11
1 files changed, 6 insertions, 5 deletions
diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc
index 118a65301..14974666e 100644
--- a/passes/hierarchy/submod.cc
+++ b/passes/hierarchy/submod.cc
@@ -151,15 +151,16 @@ struct SubmodWorker
new_wire_name = stringf("%s[%d]", wire->name.c_str(), bit.offset);
if (new_wire_port_input || new_wire_port_output) {
if (new_wire_name[0] == '$')
- do {
- std::string next_wire_name = stringf("%s\\n%d", hidden_mode ? "$submod" : ":", auto_name_counter++);
+ while (1) {
+ std::string next_wire_name = stringf("%s\\n%d", hidden_mode ? "$submod" : "", auto_name_counter++);
if (all_wire_names.count(next_wire_name) == 0) {
all_wire_names.insert(next_wire_name);
new_wire_name = next_wire_name;
+ break;
}
- } while (new_wire_name[0] == '$');
- else
- new_wire_name = stringf("$submod%s\n", new_wire_name.c_str());
+ }
+ else if (hidden_mode)
+ new_wire_name = stringf("$submod%s", new_wire_name.c_str());
}
RTLIL::Wire *new_wire = new_mod->addWire(new_wire_name);